In nanoscale architectures, chip-to-chip variation is expected to increase substantially in terms of device placement, reliability and interconnect. As a result, emerging computing technologies necessitate fundamental changes in the way architectures are designed and analyzed. The significant uncertainty associated with the assembly and operation of nanoscale devices must not only be modeled and accounted for, but actively embraced as part of the design process. In stark contrast with today's technology, probabilistic modeling and analysis are primary requirements for the successful realization of nanoscale computer architectures.

In this talk, we consider how probabilistic modeling and analysis must be applied to nanowire crossbars, the current frontrunner for the near-term realization of nanoscale architectures. Our primary focus is the problem of interfacing nanoscale wires with lithographically produced mesoscale wires via stochasticly assembled nanowire decoders. We then consider a more challenging, and more general problem of constructing reliable circuits from unreliable gates. In this context, we discuss how arbitrary circuits can be made to tolerate transient gate faults by employing error-correcting codes.